Field of the Disclosure
This disclosure relates generally to concurrent programming, and more particularly to systems and methods for improving performance for hardware transactions on multi-socket machines.
Description of the Related Art
Hardware transactional memory (HTM) supports a model of concurrent programming where the programmer specifies which code blocks should be atomic, but not how that atomicity is achieved. Some form of HTM is currently supported by processors from Intel Corporation (hereinafter “Intel”) and IBM Corporation (hereinafter “IBM”). Transactional programming models are attractive because they promise simpler code structure and better concurrency compared to traditional lock-based synchronization.
An atomic code block is called a transaction. HTM executes such transactions speculatively. For example, with HTM, if an attempt to execute a transaction commits, that atomic code block appears to have executed instantaneously and in its entirety, while if it aborts that code has no effect, and control passes to an abort handler. A condition code typically indicates why the transaction failed. One limitation of today's HTM systems is that, with some exceptions, they are best-effort implementations. In other words, HTM implementations typically make no guarantee that any transaction, however small or simple, will ever commit.
The introduction of hardware transactional memory (HTM) into commercial processors opened a door for designing and implementing scalable synchronization mechanisms. One example for such an efficient mechanism is transactional lock elision (TLE), where lock-based critical sections are executed concurrently using hardware transactions. So far, however, the effectiveness of TLE and other HTM-based mechanisms has been assessed primarily on small, single-socket machines.